公开(公告)号：US20250029892A1

公开(公告)日：2025-01-23

申请号：US18223413

申请日：2023-07-18

Applicant: Intel Corporation

Inventor： Conor P. PULS ,  Giorgio MARIOTTINI ,  Brenden ARRUDA ,  Shawna M. LIFF ,  Lei JIANG ,  Samson ODUNUGA ,  Gerardo MONTANO ,  Hannes GREVE ,  Apratim DHAR ,  Aaron M. WHITE

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

公开(公告)号：US20230420360A1

公开(公告)日：2023-12-28

申请号：US17850779

申请日：2022-06-27

Applicant: INTEL CORPORATION

Inventor： Mohit HARAN ,  Sukru YEMENICIOGLU ,  Pratik PATEL ,  Charles H. WALLACE ,  Leonard P. GULER ,  Conor P. PULS ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5226 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L27/11807 ,  H01L23/5283

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

公开(公告)号：US20230197538A1

公开(公告)日：2023-06-22

申请号：US17555654

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Mohammad Enamul KABIR ,  Conor P. PULS ,  Tofizur RAHMAN ,  Keith ZAWADZKI ,  Hannes GREVE

IPC: H01L23/04 ,  H01L27/088 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/04 ,  H01L27/088 ,  H01L23/564 ,  H01L23/5384

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a hermetic seal for a layer of transistors with metal on both sides that are on a substrate. The layer of transistors may be within a die or within a portion of a die. The hermetic seal may include a hermetic layer on one side of the layer of transistors and a hermetic layer on the opposite side of the transistors. In embodiments, one or more metal walls may be constructed through the transistor layer, with metal rings placed around either side of the layer of transistors and hermetically coupling with the two hermetic layers. Other embodiments may be described and/or claimed.

公开(公告)号：US20220399445A1

公开(公告)日：2022-12-15

申请号：US17347034

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Conor P. PULS ,  Walid M. HAFEZ ,  Sairam SUBRAMANIAN ,  Justin S. SANDFORD ,  Saurabh MORARKA ,  Sean PURSEL ,  Mohammad HASAN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

公开(公告)号：US20250006547A1

公开(公告)日：2025-01-02

申请号：US18215741

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Angel AQUINO GONZALEZ ,  Tahir GHANI ,  Conor P. PULS ,  Mitali CHINA

IPC: H01L21/762 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having removed sub-fins, and methods of fabricating integrated circuit structures having removed sub-fins, are described. For example, an integrated circuit structure includes a channel structure, and a sub-fin isolation structure in a trench beneath the channel structure, wherein there is no residual silicon portion in the trench.

公开(公告)号：US20230197779A1

公开(公告)日：2023-06-22

申请号：US17556602

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Marni NABORS ,  Mauro J. KOBRINSKY ,  Conor P. PULS ,  Kevin FISCHER ,  Curtis TSAI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L23/481

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.

公开(公告)号：US20240332301A1

公开(公告)日：2024-10-03

申请号：US18129871

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Caleb BARRETT ,  Prashant WADHWA ,  Chun-Kuo HUANG ,  Conor P. PULS ,  Daniel James HARRIS ,  Giorgio MARIOTTINI ,  Patrick MORROW

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.

公开(公告)号：US20230317563A1

公开(公告)日：2023-10-05

申请号：US17711008

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Payam AMIN ,  Tofizur RAHMAN ,  Bozidar MARINKOVIC ,  Santhosh Kumar KODURI ,  Tugba KOKER AYKOL ,  Jayeeta SEN ,  David BENNETT ,  Conor P. PULS ,  Clay MORTENSEN ,  Leslie L. CHAN ,  Hoang DOAN ,  Dolly Natalia RUIZ AMADOR

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5283 ,  H01L23/53257 ,  H01L21/76898

Abstract: Embodiments disclosed herein include a via structure and methods of forming the via structure. In an embodiment, the via structure comprises a substrate and an opening through the substrate. In an embodiment, the opening has a first portion and a second portion under the first portion. In an embodiment, the via structure further comprises a lining on sidewalls of the first portion of the opening, and a via filling the opening. In an embodiment, the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width.

公开(公告)号：US20220399334A1

公开(公告)日：2022-12-15

申请号：US17346999

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Conor P. PULS ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

Abstract: Integrated circuit structures having backside self-aligned conductive via bars, and methods of fabricating integrated circuit structures having backside self-aligned conductive via bars, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first gate electrode is around the first stack of nanowires. A second gate electrode is around the second stack of nanowires. A conductive trench contact structure is between the first gate electrode and the second gate electrode. A conductive via bar is on the conductive trench contact structure, the conductive via bar having a backside surface co-planar with a backside surface of the first and second sub-fin structures.

公开(公告)号：US20220393013A1

公开(公告)日：2022-12-08

申请号：US17339146

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sairam SUBRAMANIAN ,  Conor P. PULS ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.