公开(公告)号：US20190165789A1

公开(公告)日：2019-05-30

申请号：US16235926

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Herman Henry Schmit

IPC: H03K19/177

CPC classification number: H03K19/17796 ,  H03K19/17724 ,  H03K19/1774 ,  H03K19/17792

Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

公开(公告)号：US20180307783A1

公开(公告)日：2018-10-25

申请号：US15941983

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Vamsi Nalluri ,  Herman Henry Schmit ,  Scott J. Weber ,  Randy Huang

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04

CPC classification number: G06F17/505 ,  G06N3/04 ,  G06N3/0635 ,  G06N3/08

Abstract: Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

公开(公告)号：US11115026B2

公开(公告)日：2021-09-07

申请号：US16747408

申请日：2020-01-20

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Herman Henry Schmit

IPC: H03K19/17796 ,  H03K19/17792 ,  H03K19/17736 ,  H03K19/17724

Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

公开(公告)号：US10187064B1

公开(公告)日：2019-01-22

申请号：US15828238

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Herman Henry Schmit

IPC: H03K19/177

Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

公开(公告)号：US10860760B2

公开(公告)日：2020-12-08

申请号：US15941983

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Vamsi Nalluri ,  Herman Henry Schmit ,  Scott J. Weber ,  Randy Huang

IPC: G06F30/327 ,  G06F30/34 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

公开(公告)号：US10587273B2

公开(公告)日：2020-03-10

申请号：US16235926

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Herman Henry Schmit

IPC: H03K19/177 ,  H03K19/17796 ,  H03K19/17792 ,  H03K19/17736 ,  H03K19/17724

Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

公开(公告)号：US10303834B2

公开(公告)日：2019-05-28

申请号：US16105306

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： David Michael Lewis ,  Herman Henry Schmit

IPC: G06F17/50 ,  H03K19/00 ,  H03K5/159 ,  H03K19/0175 ,  H03K5/00

Abstract: An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.

公开(公告)号：US20190179990A1

公开(公告)日：2019-06-13

申请号：US15841064

申请日：2017-12-13

Applicant: Intel Corporation

Inventor： Herman Henry Schmit

IPC: G06F17/50 ,  G06F1/10 ,  H03K19/003 ,  H03K19/096

Abstract: The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

公开(公告)号：US20180373831A1

公开(公告)日：2018-12-27

申请号：US16105306

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： David Michael Lewis ,  Herman Henry Schmit

IPC: G06F17/50 ,  H03K19/00 ,  H03K19/0175 ,  H03K5/159 ,  H03K5/00

Abstract: An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.

公开(公告)号：US11210443B2

公开(公告)日：2021-12-28

申请号：US15841064

申请日：2017-12-13

Applicant: Intel Corporation

Inventor： Herman Henry Schmit

IPC: G06F30/3312 ,  G06F1/10 ,  H03K19/003 ,  H03K19/096 ,  H03K19/177 ,  G06F30/35 ,  G06F30/327 ,  G06F30/396 ,  G06F119/12

Abstract: The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.