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公开(公告)号:US09787264B2
公开(公告)日:2017-10-10
申请号:US15038440
申请日:2013-12-20
Applicant: Intel Corporation
Inventor: Miaobin Gao , Christine M. Krause , Hiu-Chin Wu , Hengju Cheng
CPC classification number: H03F3/45475 , H01L23/48 , H01L2224/48091 , H01L2224/48137 , H01L2924/0002 , H03F1/34 , H03F3/087 , H03F3/45183 , H03F2203/45112 , H03F2203/45206 , H03F2203/45288 , H03F2203/45528 , H03F2203/45641 , H03F2203/45646 , H03F2203/45674 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H04B3/02 , H01L2924/00014 , H01L2924/00
Abstract: Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.
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公开(公告)号:US20160301372A1
公开(公告)日:2016-10-13
申请号:US15038440
申请日:2013-12-20
Applicant: INTEL CORPORATION
Inventor: Miaobin GAO , Christine M. KRAUSE , Hiu-Chin Wu , Hengju CHENG
CPC classification number: H03F3/45475 , H01L23/48 , H01L2224/48091 , H01L2224/48137 , H01L2924/0002 , H03F1/34 , H03F3/087 , H03F3/45183 , H03F2203/45112 , H03F2203/45206 , H03F2203/45288 , H03F2203/45528 , H03F2203/45641 , H03F2203/45646 , H03F2203/45674 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H04B3/02 , H01L2924/00014 , H01L2924/00
Abstract: Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.
Abstract translation: 用于提供与可配置收发器电路的信号通信的技术和机制。 在一个实施例中,集成电路包括包括输出级和电流镜电路的收发器电路。 输出级被耦合以接收差分信号对,并且基于差分信号对提供至少一个输出信号。 在另一实施例中,配置逻辑可操作以在收发器电路的第一模式和第二模式之间进行选择。 第一模式包括电流镜电路被禁止向输出级提供电流信号,并且第一电路路径被封闭以向输出级提供电压。 第二模式包括第一电路路径是打开的,并且电流镜电路能够向输出级提供电流信号。
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