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    EXTENDED STIFFENER FOR PLATFORM MINIATURIZATION
    1.
    发明申请
    EXTENDED STIFFENER FOR PLATFORM MINIATURIZATION 审中-公开

    公开(公告)号：US20190013303A1

    公开(公告)日：2019-01-10

    申请号：US15996302

    申请日：2018-06-01

    Applicant: Intel Corporation

    Inventor： Eng Huat GOH ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Min Suet LIM ,  Khang Choong YONG ,  Howe Yin LOO

    IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L21/50 ,  H01L49/02

    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

    THREE-DIMENSIONAL DECOUPLING INTEGRATION WITHIN HOLE IN MOTHERBOARD
    2.
    发明申请
    THREE-DIMENSIONAL DECOUPLING INTEGRATION WITHIN HOLE IN MOTHERBOARD 审中-公开

    公开(公告)号：US20190394871A1

    公开(公告)日：2019-12-26

    申请号：US16481043

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Jia Yan GO ,  Min Suet LIM ,  Tin Poay CHUAH ,  Seok Ling LIM ,  Howe Yin LOO

    IPC: H05K1/02 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L21/50 ,  H05K1/18 ,  H05K1/11 ,  H05K3/30

    Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).

    DEVICE, METHOD AND SYSTEM FOR PROVIDING RECESSED INTERCONNECT STRUCTURES OF A SUBSTRATE
    3.
    发明申请
    DEVICE, METHOD AND SYSTEM FOR PROVIDING RECESSED INTERCONNECT STRUCTURES OF A SUBSTRATE 审中-公开

    公开(公告)号：US20190131227A1

    公开(公告)日：2019-05-02

    申请号：US16095916

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Howe Yin LOO ,  Sujit SHARAN ,  Tin Poay CHUAH ,  Ananth PRABHAKUMAR

    IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18

    Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

    LAPTOP ARRANGEMENT FOR HEAT CONTROL
    4.
    发明公开
    LAPTOP ARRANGEMENT FOR HEAT CONTROL 审中-公开

    公开(公告)号：US20240147654A1

    公开(公告)日：2024-05-02

    申请号：US18050502

    申请日：2022-10-28

    Applicant: Intel Corporation

    Inventor： Jiunn Shyong CHEE ,  Howe Yin LOO ,  Tin Poay CHUAH ,  Chin Kung GOH ,  Yew San LIM

    IPC: H05K7/20 ,  G06F1/20

    CPC classification number: H05K7/20136 ,  G06F1/203

    Abstract: The present disclosure is directed to a laptop arrangement including: a chassis defining a space that is divided into a first compartment and a second compartment, the first compartment including an air inlet and the second compartment including an air outlet; and a partitioning element positioned between the first and second compartments, whereby the partitioning element at least partially seals the first compartment from the second compartment and enables the second compartment to have a greater pressurization than the first compartment.

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