公开(公告)号：US10268497B2

公开(公告)日：2019-04-23

申请号：US14126894

申请日：2013-10-24

申请人： Intel Corporation

发明人： Hongbo Rong ,  Hyunchul Park ,  Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/455 ,  G06F8/41 ,  G06F8/52

摘要： Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

公开(公告)号：US09940229B2

公开(公告)日：2018-04-10

申请号：US14496621

申请日：2014-09-25

申请人： Intel Corporation

发明人： Xipeng Shen ,  Youfeng Wu ,  Cheng Wang ,  Hyunchul Park ,  Hongbo Rong

IPC分类号： G06F12/02

CPC分类号： G06F12/0238 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7207

摘要： Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.

公开(公告)号：US09495168B2

公开(公告)日：2016-11-15

申请号：US14126466

申请日：2013-05-30

申请人： Intel Corporation

发明人： Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/45

CPC分类号： G06F9/3838 ,  G06F8/434 ,  G06F8/441 ,  G06F8/443 ,  G06F9/30127 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384

摘要： In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。 存储器范围信息引用存储器内的一个或多个存储器位置。 该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作 循环和循环的后续迭代中的第二操作。 该系统还包括耦合到处理器的存储器。 描述和要求保护其他实施例。

公开(公告)号：US09239712B2

公开(公告)日：2016-01-19

申请号：US13853430

申请日：2013-03-29

申请人： Intel Corporation

发明人： Hongbo Rong ,  Hyunchul Park ,  Youfeng Wu

IPC分类号： G06F9/45

CPC分类号： G06F8/4452 ,  G06F8/433

摘要： Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.

摘要翻译： 设备和方法可以提供用于通过动态编译器来确定用于处理一个或多个循环的性能水平，并且执行代码优化以生成用于在规定时间段内实现所确定的性能水平的所述一个或多个循环的流水线调度。 在一个示例中，可以为一个或多个循环建立依赖图，并且可以基于性能水平将每个依赖图划分成多个阶段。

公开(公告)号：US09170792B2

公开(公告)日：2015-10-27

申请号：US14126463

申请日：2013-05-30

申请人： Intel Corporation

发明人： Hyunchul Park ,  Hongbo Rong ,  Youfeng Wu

IPC分类号： G06F9/45

CPC分类号： G06F8/4452 ,  G06F8/441 ,  G06F8/443 ,  G06F8/4451 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863

摘要： In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，系统包括处理器，其包括至少一个核，以执行包括S级的循环的操作。 该系统还包括阶段插入装置，用于向环路增加延迟级，以增加与循环的第一变量相关联的相应寄存器的寿命并延迟存储寄存器的内容。 该系统还包括动态随机存取存储器（DRAM）。 描述和要求保护其他实施例。

公开(公告)号：US09542211B2

公开(公告)日：2017-01-10

申请号：US14225755

申请日：2014-03-26

申请人： Intel Corporation

发明人： Cheng Wang ,  Youfeng Wu ,  Hongbo Rong ,  Hyunchul Park

IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F13/10 ,  G06F9/44

CPC分类号： G06F9/45516 ,  G06F9/4411 ,  G06F9/4552 ,  G06F13/10

摘要： In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。 当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。 描述和要求保护其他实施例。