公开(公告)号：US20210150770A1

公开(公告)日：2021-05-20

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06N3/04 ,  G06T15/00

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

公开(公告)号：US20200043217A1

公开(公告)日：2020-02-06

申请号：US16050375

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： GOKCEN CILINGIR ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JAMES HOLLAND ,  SANG-HEE LEE ,  JASON TANNER ,  MAYURESH VARERKAR ,  KAI XIAO

IPC: G06T15/00 ,  G06T9/00 ,  H04N19/597

Abstract: A mechanism is described for facilitating enhanced immersive media pipeline for correction of artifacts and clarity of objects in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to extract semantic data relating to objects in a scene captured through one or more cameras, where the objects include distortions, and form, based on the semantic data, a three-dimensional (3D) model of contents of the scene, where the contents include the objects. The one or more processors are further to encode the 3D model including the contents and the semantic data into an encoded file having encoded contents and encoded semantic data and transmit the encoded file over an immersive media pipeline to facilitate correction of the distortions and rendering the scene including the objects without the distortions.

公开(公告)号：US20230377209A1

公开(公告)日：2023-11-23

申请号：US18322194

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06T9/007 ,  G06T15/005 ,  G06T9/008 ,  G06N3/045

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.