公开(公告)号：US20160073126A1

公开(公告)日：2016-03-10

申请号：US14782593

申请日：2013-12-23

Applicant: Wenhao ZHANG ,  Yi-jen CHIU ,  Lidong XU ,  Yu HAN ,  Zhipin DENG ,  Xiaoxia CAI ,  INTEL CORPORATION

Inventor： WENHAO ZHANG ,  YI-JEN CHIU ,  LIDONG XU ,  YU HAN ,  ZHIPIN DENG ,  XIAOXIA CAI

IPC: H04N19/51 ,  H04N19/187 ,  H04N19/176

CPC classification number: H04N19/51 ,  H04N19/103 ,  H04N19/157 ,  H04N19/176 ,  H04N19/187 ,  H04N19/19 ,  H04N19/30 ,  H04N19/50 ,  H04N19/61

Abstract: Techniques for inter-layer residual prediction are described. In one embodiment, for example, an apparatus may comprise an encoding component to determine whether a predicted motion for an enhancement layer block is consistent with a predicted motion for a collocated lower-layer block, determine whether to apply inter-layer residual prediction to the enhancement layer block based on whether the predicted motion for the enhancement layer block is consistent with the predicted motion for the collocated lower-layer block, and in response to a determination that inter-layer residual prediction is to be applied to the enhancement layer block, generate a predicted residual for the enhancement layer block based on a residual for the collocated lower-layer block and generate a second-order residual for the enhancement layer block by comparing a calculated residual to the predicted residual. Other embodiments are described and claimed.

Abstract translation: 描述了层间残差预测技术。 在一个实施例中，例如，设备可以包括编码组件，以确定增强层块的预测运动是否与并置的下层块的预测运动一致，确定是否将层间残差预测应用于 增强层块基于增强层块的预测运动是否与所配置的下层块的预测运动一致，并且响应于将层间残差预测应用于增强层块的确定， 基于所配置的下层块的残差生成用于增强层块的预测残差，并通过将计算出的残差与预测残差进行比较来生成增强层块的二阶残差。 描述和要求保护其他实施例。

公开(公告)号：US20230377209A1

公开(公告)日：2023-11-23

申请号：US18322194

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06T9/007 ,  G06T15/005 ,  G06T9/008 ,  G06N3/045

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

公开(公告)号：US20210150770A1

公开(公告)日：2021-05-20

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06N3/04 ,  G06T15/00

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

公开(公告)号：US20160182915A1

公开(公告)日：2016-06-23

申请号：US14580931

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： SANG-HEE LEE ,  JAMES M. HOLLAND ,  LIDONG XU ,  HONG JIANG

IPC: H04N19/513 ,  H04N19/543 ,  H04N19/56

CPC classification number: H04N19/521 ,  H04N19/43 ,  H04N19/533 ,  H04N19/543 ,  H04N19/56

Abstract: Techniques related to providing motion estimation for arbitrary pixel block shapes are discussed. Such techniques may include generating a distortion mesh for a pixel block based on multiple calls to a motion estimation such that the distortion mesh includes distortion values associated with regions of the pixel block, a seed motion vector, and candidate motion vectors, and determining a best motion vector for the pixel block based on the distortion mesh.

Abstract translation: 讨论了与提供任意像素块形状的运动估计有关的技术。 这样的技术可以包括基于对运动估计的多次调用来生成用于像素块的失真网格，使得失真网格包括与像素块的区域，种子运动矢量和候选运动矢量相关联的失真值，并且确定最佳 基于失真网格的像素块的运动矢量。