COMPENSATION FOR HOLD-OVER ERRORS IN DISTRIBUTED CLOCK SYNCHRONIZATION

    公开(公告)号:US20190205272A1

    公开(公告)日:2019-07-04

    申请号:US16299905

    申请日:2019-03-12

    Abstract: Examples include a method of compensating for hold-over errors in a distributed clock synchronization system. When a first computing platform has a synchronized connection with a second computing platform, a clock sync component obtains a first temperature of a network input/output (I/O) device of the first computing platform and a frequency adjustment value of a clock of the network I/O device and stores the temperature and the frequency adjustment value in an entry in a clock synchronization database. When the first computing platform does not have a synchronized connection with the second computing platform (e.g., hold-over mode), the clock sync component obtains a second temperature of the network I/O device, searches the clock synchronization database for the entry where the first temperature is closest to the second temperature, and when the entry is found, obtains the frequency adjustment value and adjusts the clock of the network I/O device using the frequency adjustment value.

    CONNECTING AN EXTERNAL PHY DEVICE TO A MAC DEVICE USING A MANAGEMENT DATA INPUT/OUTPUT INTERFACE

    公开(公告)号:US20190042484A1

    公开(公告)日:2019-02-07

    申请号:US16129318

    申请日:2018-09-12

    Abstract: Examples include connecting an external physical layer device to a media access control device by determining a mode of a communications link between the external physical layer device and the media access control device; and when the mode of the communications link is serial gigabit media independent interface (SGMII), enabling an inter-integrated circuit (I2) interface between the external physical layer device and the media access control device, and setting a destination for management data input/output (MDIO) transactions to the external physical layer device.

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