公开(公告)号：US20190205272A1

公开(公告)日：2019-07-04

申请号：US16299905

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Zoltan FODOR ,  Jakub FORNAL

IPC: G06F13/16 ,  G06F16/903 ,  G06F13/38 ,  G06F13/12

CPC classification number: G06F13/1689 ,  G06F13/126 ,  G06F13/385 ,  G06F16/903 ,  G06F2213/0026

Abstract: Examples include a method of compensating for hold-over errors in a distributed clock synchronization system. When a first computing platform has a synchronized connection with a second computing platform, a clock sync component obtains a first temperature of a network input/output (I/O) device of the first computing platform and a frequency adjustment value of a clock of the network I/O device and stores the temperature and the frequency adjustment value in an entry in a clock synchronization database. When the first computing platform does not have a synchronized connection with the second computing platform (e.g., hold-over mode), the clock sync component obtains a second temperature of the network I/O device, searches the clock synchronization database for the entry where the first temperature is closest to the second temperature, and when the entry is found, obtains the frequency adjustment value and adjusts the clock of the network I/O device using the frequency adjustment value.

公开(公告)号：US20190042484A1

公开(公告)日：2019-02-07

申请号：US16129318

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Jakub FORNAL ,  Zoltan FODOR

IPC: G06F13/10

Abstract: Examples include connecting an external physical layer device to a media access control device by determining a mode of a communications link between the external physical layer device and the media access control device; and when the mode of the communications link is serial gigabit media independent interface (SGMII), enabling an inter-integrated circuit (I2) interface between the external physical layer device and the media access control device, and setting a destination for management data input/output (MDIO) transactions to the external physical layer device.

公开(公告)号：US20240204899A1

公开(公告)日：2024-06-20

申请号：US18426209

申请日：2024-01-29

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Zoltan FODOR

IPC: H04J3/06

CPC classification number: H04J3/0667 ,  H04J3/0682

Abstract: Examples described herein relate to a first network interface controller comprising a first network interface, first timer, and a first signal transceiver and circuitry to reduce offset between the first timer of the first network interface controller and a second timer of a second network interface controller. The circuitry to reduce offset between the first timer of the first network interface controller and a second timer of a second network interface controller based on a first signal transmitted over a communication line from the first signal transceiver to the second network interface controller and also based on the first signal transmitted from the second network interface controller back to the first network interface controller over the communication line.