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1.发明申请公开(公告)号：US20190214276A1
公开(公告)日：2019-07-11
申请号：US15865471
申请日：2018-01-09
Applicant: Intel Corporation
Inventor： Amit K. Jain , Sameer Shekhar , Kaladhar Radhakrishnan
IPC: H01L21/56 , H05K1/16 , H05K1/02 , H01L23/64 , H02J50/10 , H01F27/24 , H01F17/04 , H01F17/00 , H01L21/48
Abstract: Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.
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公开(公告)号：US20170373587A1
公开(公告)日：2017-12-28
申请号：US15195671
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Chin Lee Kuan , Sameer Shekhar , Amit K. Jain
CPC classification number: H02M1/14 , G06F1/26 , H02M2001/009 , H05K1/0231
Abstract: Methods and apparatus relating to a compact partitioned capacitor design for multiple voltage and/or load domains (e.g., with improved decoupling) are described. In an embodiment, a capacitor provides substrate decoupling for a plurality of loads. Moreover, the capacitor is capable of decoupling two or more voltage domains. Furthermore, in some embodiments the capacitor is capable of decoupling two or more voltage domains and mitigating self-noise and/or cross-noise between them. Other embodiments are also disclosed and claimed.
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3.发明申请公开(公告)号：US20170293445A1
公开(公告)日：2017-10-12
申请号：US15093687
申请日：2016-04-07
Applicant: Intel Corporation
Inventor： Amit K. Jain , Sameer Shekhar
Abstract: Methods and apparatus relating to dynamic voltage regulator sensing and/or reference voltage setting techniques for multiple gated loads are described. In an embodiment, voltage regulator logic is coupled to one or more loads. Each of the one or more loads is in a separate power domain. The voltage regulator logic controls a sensed voltage from the one or more loads in response to a power gate control signal. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20170288647A1
公开(公告)日：2017-10-05
申请号：US15087250
申请日：2016-03-31
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Pooja Nukala
IPC: H03K3/011 , H01L25/065 , H05K1/18 , H01L23/00 , H01L23/498
CPC classification number: H01L25/0655 , H01L23/49838 , H01L24/17 , H01L2224/16225 , H01L2924/1304 , H01L2924/13091 , H01L2924/1432 , H01L2924/15311 , H01L2924/19011 , H01L2924/19043 , H01L2924/19101 , H03K19/0005 , H05K1/181 , H05K2201/10166 , H05K2201/10234 , H05K2201/10318 , H05K2201/10378
Abstract: Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.
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公开(公告)号：US10972001B2
公开(公告)日：2021-04-06
申请号：US16102203
申请日：2018-08-13
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Ravi Sankar Vunnam
Abstract: Some embodiments include apparatuses having a switching circuit included in a buck converter; an output node; an inductor including a first portion having a first terminal coupled to the switching circuit, a second portion having a second terminal coupled to the output node, and a third terminal between the first and second portions; and a capacitor coupled to the second terminal, the second terminal to couple to a first additional capacitor, and the third terminal to couple to a second additional capacitor.
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Patent Agency Ranking
公开(公告)号：US10719109B2
公开(公告)日：2020-07-21
申请号：US15627159
申请日：2017-06-19
Applicant: Intel Corporation
Inventor： Amit K. Jain , Chin Lee Kuan , Sameer Shekhar
IPC: G06F1/26
Abstract: Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.
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公开(公告)号：US20200052583A1
公开(公告)日：2020-02-13
申请号：US16102203
申请日：2018-08-13
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Ravi Sankar Vunnam
Abstract: Some embodiments include apparatuses having a switching circuit included in a buck converter; an output node; an inductor including a first portion having a first terminal coupled to the switching circuit, a second portion having a second terminal coupled to the output node, and a third terminal between the first and second portions; and a capacitor coupled to the second terminal, the second terminal to couple to a first additional capacitor, and the third terminal to couple to a second additional capacitor.
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公开(公告)号：US10453705B2
公开(公告)日：2019-10-22
申请号：US15865471
申请日：2018-01-09
Applicant: Intel Corporation
Inventor： Amit K. Jain , Sameer Shekhar , Kaladhar Radhakrishnan
IPC: H01L21/56 , H01F17/04 , H02J50/10 , H01F27/24 , H01L23/64 , H01L21/48 , H01F17/00 , H05K1/16 , H05K1/02
Abstract: Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.
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公开(公告)号：US10014692B2
公开(公告)日：2018-07-03
申请号：US14575900
申请日：2014-12-18
Applicant: Intel Corporation
Inventor： Amit K. Jain , Sameer Shekhar
CPC classification number: H02J4/00 , H01F5/00 , H03H1/0007 , H03H7/00 , H03H7/09 , H03H7/1725 , H03H7/48 , H03H2001/0078
Abstract: Embodiments include apparatuses, methods, and systems with cross-coupling noise reduction in circuits. In embodiments, a circuit may include a common inductor and a negatively coupled inductor pair connected or coupled between the first inductor and a first load and a second load. The negatively coupled inductor pair may include a first and a second inductor. The first inductor may be connected or coupled to the first load and the second inductor may be connected or coupled to the second load to reduce cross-coupling noise between the first load and the second load. Examples of passive structures that may be used to implement the circuit are also described. Other embodiments may also be described and claimed.
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10.发明申请公开(公告)号：US20160371216A1
公开(公告)日：2016-12-22
申请号：US14742695
申请日：2015-06-17
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain
CPC classification number: G06F13/4068 , G06F1/26 , H01L23/642 , H01L25/16 , H05K1/0231 , H05K1/162 , H05K2201/10015
Abstract: Methods and apparatus relating to capacitor interconnections and/or volume re-capture for voltage noise reduction are described. In an embodiment, an interconnection capacitor is coupled to voltage regulator logic. The interconnection capacitor provides substrate decoupling for a plurality of loads. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了与电容器互连和/或电压噪声降低的体积再捕获有关的方法和装置。 在一个实施例中，互连电容器耦合到电压调节器逻辑。 互连电容器为多个负载提供衬底去耦。 还公开并要求保护其他实施例。
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