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公开(公告)号：US20190146714A1
公开(公告)日：2019-05-16
申请号：US16234655
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Vidhya Krishnan , Niranjan Cooray , Prasoonkumar Surti , John Feit
Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.
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公开(公告)号：US11593909B2
公开(公告)日：2023-02-28
申请号：US17475147
申请日：2021-09-14
Applicant: Intel Corporation
Inventor： Ravishankar Iyer , Selvakumar Panneer , Carl S. Marshall , John Feit , Venkat R. Gokulrangan
IPC: G06T1/20 , G06F9/48 , G06F9/50 , A63F13/358
Abstract: An apparatus and method for scheduling threads on local and remote processing resources. For example, one embodiment of an apparatus comprises: a local graphics processor to execute threads of an application; graphics processor virtualization circuitry and/or logic to generate a virtualized representation of a local processor; a scheduler to identify a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor; the scheduler to schedule the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to Cloud-based processing resources associated with the virtualized representation of the local processor; and the local graphics processor to combine first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the Cloud-based processing resources to render an image frame.
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公开(公告)号：US20220148123A1
公开(公告)日：2022-05-12
申请号：US17475147
申请日：2021-09-14
Applicant: Intel Corporation
Inventor： Ravishankar Iyer , Selvakumar Panneer , Carl S. Marshall , John Feit , Venkat R. Gokulrangan
Abstract: An apparatus and method for scheduling threads on local and remote processing resources. For example, one embodiment of an apparatus comprises: a local graphics processor to execute threads of an application; graphics processor virtualization circuitry and/or logic to generate a virtualized representation of a local processor; a scheduler to identify a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor; the scheduler to schedule the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to Cloud-based processing resources associated with the virtualized representation of the local processor; and the local graphics processor to combine first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the Cloud-based processing resources to render an image frame.
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公开(公告)号：US11127107B2
公开(公告)日：2021-09-21
申请号：US16588855
申请日：2019-09-30
Applicant: Intel Corporation
Inventor： Ravishankar Iyer , Selvakumar Panneer , Carl S. Marshall , John Feit , Venkat R. Gokulrangan
IPC: G06T1/20 , G06F9/48 , G06F9/50 , A63F13/358
Abstract: An apparatus and method for scheduling threads on local and remote processing resources. For example, one embodiment of an apparatus comprises: a local graphics processor to execute threads of an application; graphics processor virtualization circuitry and/or logic to generate a virtualized representation of a local processor; a scheduler to identify a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor; the scheduler to schedule the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to Cloud-based processing resources associated with the virtualized representation of the local processor; and the local graphics processor to combine first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the Cloud-based processing resources to render an image frame.
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公开(公告)号：US10997772B1
公开(公告)日：2021-05-04
申请号：US16724764
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Michael Apodaca , John Feit , David Cimini , Thomas Raoux , Konstantin Levit-Gurevich
IPC: G06T15/00
Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.
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Patent Agency Ranking
公开(公告)号：US20240311951A1
公开(公告)日：2024-09-19
申请号：US18478286
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Selvakumar Panneer , Sarthak Rajesh Shah , Nilesh Jain , John Feit
CPC classification number: G06T1/20 , G06F9/5038
Abstract: Described herein is a graphics processor configured to perform time based frame predication to bypass execution of a command buffer based on a comparison with time stamps stored in a time stamp buffer that tracks execution time for command buffers. The graphics processors can bypass a frame that will not complete in time for a target display update and trigger neural frame generation to generate the frame data for the bypassed command buffer. Dynamic render scaling is also described.
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公开(公告)号：US20240307773A1
公开(公告)日：2024-09-19
申请号：US18478201
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Selvakumar Panneer , John Feit , Sarthak Rajesh Shah , SungYe Kim , Nilesh Jain
IPC: A63F13/52
CPC classification number: A63F13/52 , A63F2300/66
Abstract: Described herein is a technique to enhance the responsiveness of gameplay for a 3D gaming application while maintaining the ability to enqueue multiple frames for processing on the GPU. Each frame or a set of workloads within a frame is submitted to the GPU with predication, such that the indicated rendering and resource manipulation commands are not actually performed if the predication condition is enabled. A low latency command can be submitted to the GPU via a copy engine command queue. The command will cause the copy engine to enable or disable predication for command buffers in the command queue. When predication for queued command buffers is enabled, command buffers for workloads that are not related to the workload that is generated in response to the user input are bypassed. High priority command buffers that include workloads generated in response to user input can then be executed immediately.
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公开(公告)号：US20230140640A1
公开(公告)日：2023-05-04
申请号：US17518328
申请日：2021-11-03
Applicant: Intel Corporation
Inventor： Stav Gurtovoy , Abhishek Venkatesh , Michael Apodaca , Travis Schluessler , John Feit
IPC: G06T15/00 , G06T1/20 , G06T1/60 , H01L25/065 , H01L23/00 , H01L23/31 , H01L23/538
Abstract: Methods, systems and apparatuses may provide for technology that marks a graphics resource as a flush candidate during a current frame, conducts an early flush of a command buffer from the graphics resource if a write event is detected with respect to the graphics resource during a subsequent frame, and bypasses the early flush if the write event is not detected with respect to the graphics resource during the subsequent frame. In one example, the graphics resource is marked as the flush candidate in response to a read back operation of the host processor with respect to the graphics resource, wherein the read back operation retrieves a query result and/or maps a staging resource.
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公开(公告)号：US20220301228A1
公开(公告)日：2022-09-22
申请号：US17357038
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Stephen Junkins , Sreenivas Kothandaraman , Prasoonkumar Surti , Srihari Pratapa , William Hux , John Feit
Abstract: Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.
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公开(公告)号：US12223682B2
公开(公告)日：2025-02-11
申请号：US17357038
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Stephen Junkins , Sreenivas Kothandaraman , Prasoonkumar Surti , Srihari Pratapa , William Hux , John Feit
Abstract: Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.
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