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    NETWORK FOR STRUCTURE-BASED TEXT-TO-IMAGE GENERATION
    1.
    发明公开
    NETWORK FOR STRUCTURE-BASED TEXT-TO-IMAGE GENERATION 审中-公开

    公开(公告)号：US20240185493A1

    公开(公告)日：2024-06-06

    申请号：US18400561

    申请日：2023-12-29

    申请人： Intel Corporation

    发明人： Peixi Xiong ,  Nilesh Jain

    IPC分类号： G06T11/60 ,  G06F40/205 ,  G06F40/284

    CPC分类号： G06T11/60 ,  G06F40/205 ,  G06F40/284

    摘要： Technology as described herein provides for generating an image via a generator network, including extracting structural relationship information from a text prompt, wherein the structural relationship information includes sentence features and token features, generating encoded text features based on the sentence features and on relation-related tokens, wherein the relation-related tokens are identified based on parsing text dependency information in the token features, and generating an output image based on combining, via self attention and cross-attention layers, the encoded text features and encoded image features from an input image canvas. Embodiments further include applying a gating function to modify image features based on text features. The self attention and cross-attention layers can be applied via a cross-modality network, the gating function can be applied via a residual gating network, and the relation-related tokens can be further identified via an attention matrix.

    METHODS AND APPARATUS TO GENERATE OPTIMIZED MODELS FOR INTERNET OF THINGS DEVICES
    5.
    发明申请
    METHODS AND APPARATUS TO GENERATE OPTIMIZED MODELS FOR INTERNET OF THINGS DEVICES 审中-公开

    公开(公告)号：US20190140911A1

    公开(公告)日：2019-05-09

    申请号：US16236290

    申请日：2018-12-28

    申请人： Intel Corporation

    发明人： Nilesh Jain ,  Vui Seng Chua ,  Fahim Mohammad ,  Anindya Paul

    IPC分类号： H04L12/24 ,  G06N20/00 ,  G06N7/00 ,  H04L12/26 ,  H04L29/08

    摘要： Example systems, methods, and apparatus to generate optimized models for Internet of Things device are disclosed. An example apparatus includes a data receiver to collect data from a sensor of an internet of things device based a first sampling frequency and a buffer having a first buffer size; a model trainer to train a model based on the data collected from the sensor; a buffer analyzer to select a second sampling frequency and to reduce the buffer to a second buffer size, the model trainer to update the model based on the second buffer size; and a platform analyzer to: determine a duration of time that that internet of things device will take to analyze sensor data based on the updated model.

    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO OPTIMIZE RESOURCES IN EDGE NETWORKS
    7.
    发明公开
    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO OPTIMIZE RESOURCES IN EDGE NETWORKS 审中-公开

    公开(公告)号：US20240007414A1

    公开(公告)日：2024-01-04

    申请号：US18039166

    申请日：2021-06-25

    申请人： Intel Corporation

    发明人： Nilesh Jain ,  Rajesh Poornachandran ,  Eriko Nurvitadhi ,  Anahita Bhiwandiwalla ,  Juan Pablo Munoz ,  Ravishankar Iyer ,  Chaunte W. Lacewell

    IPC分类号： H04L47/726 ,  H04L47/2425 ,  H04L47/765

    CPC分类号： H04L47/726 ,  H04L47/2425 ,  H04L47/765

    摘要： Methods, apparatus, systems, and articles of manufacture are disclosed to optimize resources in edge networks. An example apparatus includes agent managing circuitry to invoke an exploration agent to identify platform resource devices, select a first one of the identified platform resource devices, and generate first optimization metrics for the workload corresponding to the first one of the identified platform resource devices, the first optimization metrics corresponding to a first path. The example agent is to further select a second one of the identified platform resource devices, generate second optimization metrics for the workload corresponding to the second one of the identified platform resource devices, the second optimization metrics corresponding to a second path. The example apparatus also includes benchmark managing circuitry to embed second semantic information to the workload, the second semantic information including optimized graph information and platform structure information corresponding to the second one of the identified platform resource devices, and reconfiguration managing circuitry to select the first path or the second path during runtime based on (a) service level agreement (SLA) information and (b) utilization information corresponding to the first and second identified platform resource devices.

    SYSTEM FOR UNIVERSAL HARDWARE-NEURAL NETWORK ARCHITECTURE SEARCH (CO-DESIGN)
    10.
    发明申请
    SYSTEM FOR UNIVERSAL HARDWARE-NEURAL NETWORK ARCHITECTURE SEARCH (CO-DESIGN) 有权

    公开(公告)号：US20220108054A1

    公开(公告)日：2022-04-07

    申请号：US17552955

    申请日：2021-12-16

    申请人： Intel Corporation

    发明人： Yash Akhauri ,  Nilesh Jain ,  Juan Pablo Munoz Chiabrando ,  Adithya M. Niranjan

    IPC分类号： G06F30/27

    摘要： An architecture search system evaluates a search space of neural network and hardware architectures with a plurality of candidate controllers. Each controller attempts to identify an optimized architecture using a different optimization algorithm. To identify a controller for the search space, the architecture search system samples subspaces of the search space having a portion of the neural network search space and a portion of the hardware search space. For each subspace, candidate controllers are scored with respect to the optimized design determined by the respective candidate controllers. Using the scores for the various candidate controllers across the sampled subspaces, a controller is selected to optimize the overall network architecture search space.