公开(公告)号：US10957096B2

公开(公告)日：2021-03-23

申请号：US16447397

申请日：2019-06-20

申请人： Intel Corporation

发明人： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC分类号： G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60

摘要： Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US20200073810A1

公开(公告)日：2020-03-05

申请号：US16566188

申请日：2019-09-10

申请人： Intel Corporation

发明人： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC分类号： G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06T1/20 ,  G06F9/38 ,  G06F12/0855 ,  G06F12/0811

摘要： Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US10360717B1

公开(公告)日：2019-07-23

申请号：US15858396

申请日：2017-12-29

申请人： Intel Corporation

发明人： John G. Gierach ,  Travis Schluessler ,  Thomas F. Raoux ,  Peng Guo

IPC分类号： G06F9/38 ,  G06T1/20 ,  G06T15/00

摘要： An apparatus and method for splitting shaders. For example, one embodiment of a method comprises: receiving a request for compilation of a shader in a graphics processing environment; determining whether there is sufficient work associated with the shader to justify splitting the shader into two or more blocks of program code; evaluating the program code of the shader to identify dependencies between the blocks of program code if there is sufficient work; subdividing the shader into the two or more blocks in accordance with the identified dependencies; and individually executing the two or more blocks of code on a graphics processor. In addition, one embodiment includes the operations of determining whether any of the regions that can be subdivided are likely to run faster with different machine configurations than if the shader is executed without being subdivided, and subdividing the shader only for those regions that are likely to run faster with different machine configurations.

公开(公告)号：US20180293787A1

公开(公告)日：2018-10-11

申请号：US15483409

申请日：2017-04-10

申请人： Intel Corporation

发明人： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC分类号： G06T15/80 ,  G06T15/00

CPC分类号： G06T15/005 ,  G06T15/30 ,  G06T15/40

摘要： Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US11776195B2

公开(公告)日：2023-10-03

申请号：US17463320

申请日：2021-08-31

申请人： Intel Corporation

发明人： John G. Gierach ,  Karthik Vaidyanathan ,  Thomas F. Raoux

IPC分类号： G06T15/00 ,  G06F9/48

CPC分类号： G06T15/005 ,  G06F9/4887

摘要： Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.

公开(公告)号：US20220206990A1

公开(公告)日：2022-06-30

申请号：US17561427

申请日：2021-12-23

申请人： Intel Corporation

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US11182296B2

公开(公告)日：2021-11-23

申请号：US16566188

申请日：2019-09-10

申请人： Intel Corporation

发明人： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC分类号： G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0855 ,  G06T1/20

摘要： Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US11107263B2

公开(公告)日：2021-08-31

申请号：US16190021

申请日：2018-11-13

申请人： Intel Corporation

发明人： John G. Gierach ,  Karthik Vaidyanathan ,  Thomas F. Raoux

IPC分类号： G06T15/00 ,  G06F9/48

摘要： Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.

公开(公告)号：US10573055B2

公开(公告)日：2020-02-25

申请号：US15693084

申请日：2017-08-31

申请人： Intel Corporation

发明人： John G. Gierach ,  Darrel K. Palke ,  Travis T. Schluessler ,  Prasoonkumar Surti

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06T15/40 ,  G06T15/20 ,  G06T1/60

摘要： An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware.

公开(公告)号：US10452552B2

公开(公告)日：2019-10-22

申请号：US15488988

申请日：2017-04-17

申请人： Intel Corporation

发明人： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC分类号： G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0855 ,  G06F9/38 ,  G06T1/20

摘要： Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.