公开(公告)号：US20220254999A1

公开(公告)日：2022-08-11

申请号：US17682297

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Srivatsan VENKATESAN ,  Davide MANTEGAZZA ,  John GORMAN ,  Iniyan Soundappa ELANGO ,  Davide FUGAZZA ,  Andrea REDAELLI ,  Fabio PELLIZZER

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

公开(公告)号：US20210335419A1

公开(公告)日：2021-10-28

申请号：US17368634

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Davide MANTEGAZZA ,  Kyung Jean YOON ,  John GORMAN ,  Dany-Sebastien LY-GAGNON

IPC: G11C13/00 ,  G11C11/56

Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.