公开(公告)号：US20220254999A1

公开(公告)日：2022-08-11

申请号：US17682297

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Srivatsan VENKATESAN ,  Davide MANTEGAZZA ,  John GORMAN ,  Iniyan Soundappa ELANGO ,  Davide FUGAZZA ,  Andrea REDAELLI ,  Fabio PELLIZZER

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

公开(公告)号：US20200303463A1

公开(公告)日：2020-09-24

申请号：US16361030

申请日：2019-03-21

Applicant: Intel Corporation

Inventor： Andrea REDAELLI

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A three-dimensional (3D) memory device includes multiple decks of memory cells. Each deck includes layers of material, including a layer of storage material (e.g., a phase change material). Each deck also includes an interlayer between the phase change material and conductive access lines. The interlayer can include, for example, one or more of tungsten, carbon, silicon, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and titanium silicon nitride. In one such example, the interlayer includes tungsten silicon nitride (WSiN). The interlayers of different decks have different properties, such as different thicknesses or resistivities, to reduce or eliminate the deck-to-deck reset current offset.

公开(公告)号：US20190043580A1

公开(公告)日：2019-02-07

申请号：US16143033

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Agostino PIROVANO ,  Hernan A. CASTRO ,  Innocenzo TORTORELLI ,  Andrea REDAELLI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/73 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/141

Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.

公开(公告)号：US20190043807A1

公开(公告)日：2019-02-07

申请号：US16024834

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Andrea REDAELLI ,  D. Ross ECONOMY ,  Mihir BOHRA

IPC: H01L23/532 ,  G11C8/14 ,  G11C7/18 ,  H01L21/3205 ,  H01L23/522

Abstract: A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.

公开(公告)号：US20180286921A1

公开(公告)日：2018-10-04

申请号：US15474154

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andrea REDAELLI ,  Innocenzo TORTORELLI ,  Fabio PELLIZZER ,  Agostino PIROVANO ,  DerChang KAU

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.