公开(公告)号：US20210304817A1

公开(公告)日：2021-09-30

申请号：US16828860

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Davide MANTEGAZZA ,  Kiran PANGAL

IPC: G11C13/00 ,  G11C29/12 ,  G11C29/50 ,  G11C29/44

Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.

公开(公告)号：US20200159424A1

公开(公告)日：2020-05-21

申请号：US16751863

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Ashir G. SHAH ,  Prashant DAMLE ,  Davide MANTEGAZZA

IPC: G06F3/06

Abstract: Deck offset techniques for multi-deck non-volatile memory can reduce the average raw bit error rate (RBER) for a memory system. Deck offset can enable accessing different physical decks for the same input deck address. In one example in a system with multiple memory components, different physical decks are accessed across multiple memory components for the same logical deck address. In one example in a system with one memory component, different physical decks are accessed across multiple partitions of the same memory component.

公开(公告)号：US20210335419A1

公开(公告)日：2021-10-28

申请号：US17368634

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Davide MANTEGAZZA ,  Kyung Jean YOON ,  John GORMAN ,  Dany-Sebastien LY-GAGNON

IPC: G11C13/00 ,  G11C11/56

Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.

公开(公告)号：US20220254999A1

公开(公告)日：2022-08-11

申请号：US17682297

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Srivatsan VENKATESAN ,  Davide MANTEGAZZA ,  John GORMAN ,  Iniyan Soundappa ELANGO ,  Davide FUGAZZA ,  Andrea REDAELLI ,  Fabio PELLIZZER

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

公开(公告)号：US20210098034A1

公开(公告)日：2021-04-01

申请号：US16584339

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Davide MANTEGAZZA

IPC: G11C7/10 ,  G11C8/08 ,  G11C7/12 ,  G11C8/10

Abstract: Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.