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    CRC update mechanism
    3.
    发明授权
    CRC update mechanism 有权

    公开(公告)号：US10785150B2

    公开(公告)日：2020-09-22

    申请号：US14866180

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

    IPC: H04L12/741 ,  H04L29/06

    Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.

    PIPELINED HASH TABLE WITH REDUCED COLLISIONS
    4.
    发明申请
    PIPELINED HASH TABLE WITH REDUCED COLLISIONS 审中-公开

    公开(公告)号：US20200159654A1

    公开(公告)日：2020-05-21

    申请号：US16751406

    申请日：2020-01-24

    Applicant: Intel Corporation

    Inventor： Sanjeev Jain ,  Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

    IPC: G06F12/02 ,  G06F9/54

    Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.

    Single-lane, twenty-five gigabit ethernet
    6.
    发明授权
    Single-lane, twenty-five gigabit ethernet 有权
    单通道，二十五千兆以太网

    公开(公告)号：US09426096B2

    公开(公告)日：2016-08-23

    申请号：US14284034

    申请日：2014-05-21

    Applicant: Intel Corporation

    Inventor： Alain Gravel ,  Robert G. Southworth ,  Jonathan A. Dama ,  Ilango S. Ganga ,  Matthew J. Webb

    IPC: H04L12/931 ,  H04L7/033 ,  H04L12/825 ,  H04L1/00 ,  H04L12/413

    CPC classification number: H04L47/25 ,  H04J3/0697 ,  H04L1/00 ,  H04L1/0002 ,  H04L1/0041 ,  H04L1/0045 ,  H04L7/033 ,  H04L7/0331 ,  H04L12/413 ,  H04L25/14 ,  H04L25/49 ,  H04L49/352

    Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

    Abstract translation: 用于高速数据传输的技术，包括具有耦合到物理介质依赖/物理介质连接（PMD / PMA）子层的通信通道的网络端口逻辑，物理编码子层（PCS）和媒体访问控制（MAC）子层 。 通信通道以25吉比特每秒的线速度接收串行二进制数据。 PMD / PMA将串行二进制数据转换为并行数据，并且PCS使用也用于较慢线速度（例如10吉比特每秒）的线路代码来解码并行数据。 网络端口逻辑可以包括四个独立的通信通道，每个通信通道耦合到专用PMD / PMA，PCS和MAC。 网络端口逻辑还可以包括多通道PCS和多通道MAC，用于接收和发送在四个通信通道上划分的数据。 描述和要求保护其他实施例。

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