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    NETWORK COMMUNICATION PRIORITIZATION BASED on AWARENESS of CRITICAL PATH of a JOB
    2.
    发明申请
    NETWORK COMMUNICATION PRIORITIZATION BASED on AWARENESS of CRITICAL PATH of a JOB 审中-公开

    公开(公告)号：US20190044883A1

    公开(公告)日：2019-02-07

    申请号：US15868110

    申请日：2018-01-11

    Applicant: Intel Corporation

    Inventor： Janusz Piotr Jurski ,  Jonathan Eastep ,  Keith D. Underwood ,  Madhusudhan Rangarajan

    IPC: H04L12/911 ,  H04L12/927 ,  H04L29/08

    Abstract: In multi-processor systems, some large jobs are performed by dividing the job into multiple tasks, having each task executed in parallel by separate nodes, and combining or synchronizing the results into a final answer. When communications between nodes represent a significant portion of total performance, techniques may be used to monitor and balance communications between the nodes so that the tasks will be completed at approximately the same time, thereby accelerating the completion of the job and avoiding wasting time and power by having some processors sit idle while waiting for other processors to catch up. Multiple synchronization points may be set up between the start and finish of task execution, to that mid-course corrections may be made.

    WORKLOAD AWARE POWER LIMITING AND MULTIPLE-INPUT MULTIPLE-OUTPUT CONTROL
    5.
    发明申请
    WORKLOAD AWARE POWER LIMITING AND MULTIPLE-INPUT MULTIPLE-OUTPUT CONTROL 有权

    公开(公告)号：US20210124404A1

    公开(公告)日：2021-04-29

    申请号：US17074288

    申请日：2020-10-19

    Applicant: Intel Corporation

    Inventor： Ali Mohammad ,  Asma Al-Rawi ,  Ujjwal Gupta ,  Federico Ardanaz ,  Jonathan Eastep

    IPC: G06F1/28 ,  G06F1/3296 ,  G06N20/00

    Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

    ACCURATE VOLTAGE CONTROL TO ENHANCE POWER PERFORMANCE OF CIRCUITS
    8.
    发明申请
    ACCURATE VOLTAGE CONTROL TO ENHANCE POWER PERFORMANCE OF CIRCUITS 审中-公开

    公开(公告)号：US20190041930A1

    公开(公告)日：2019-02-07

    申请号：US15856154

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： Kelly Livingston ,  Federico Ardanaz ,  Dmitry Lukianchenko ,  Fuat Keceli ,  Jonathan Eastep

    IPC: G06F1/26

    Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.

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