公开(公告)号：US09164573B2

公开(公告)日：2015-10-20

申请号：US13785115

申请日：2013-03-05

申请人： Intel Corporation

发明人： Douglas D. Boom ,  Jordan J. Rodgers

IPC分类号： G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/32 ,  G06F1/3225 ,  Y02D10/122

摘要： In an embodiment, the present invention includes a multicore processor with a front end unit including a fetch unit to fetch instructions and a decode unit to decode the fetched instructions into decoded instructions, a first core coupled to the front end unit to independently execute at least some of the decoded instructions, and a second core coupled to the front end unit to independently execute at least some of the decoded instructions. The second core may have a second power consumption level greater than a power consumption level of the first core and also heterogeneous from the first core. The processor may further include an arbitration logic coupled to the first and second cores to enable the second core to begin execution responsive to a start processor instruction present in the front end unit. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有前端单元的多核处理器，前端单元包括用于取指令的提取单元和解码单元，用于将获取的指令解码为经解码的指令;耦合到前端单元的第一核至少独立地执行 解码指令中的一些，以及耦合到前端单元以独立地执行至少一些解码指令的第二核心。 第二核可以具有大于第一核的功率消耗水平的第二功率消耗水平，并且还具有来自第一核的异质。 处理器还可以包括耦合到第一和第二核的仲裁逻辑，以使得第二核能够响应于前端单元中存在的起始处理器指令开始执行。 描述和要求保护其他实施例。