公开(公告)号：US20250098230A1

公开(公告)日：2025-03-20

申请号：US18370725

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Sean PURSEL ,  Dimitri KIOUSSIS ,  Lukas BAUMGARTEL ,  Mahdi AHMADI ,  Cortnie S. VOGELSBERG ,  Mengcheng LU ,  Omar Kyle HITE ,  Justin E. MUELLER ,  Lily Mao

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having dual stress gates are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. An NMOS gate electrode is over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. A PMOS gate electrode is over the second vertical stack of horizontal nanowires, the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. The tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.

公开(公告)号：US20230101107A1

公开(公告)日：2023-03-30

申请号：US17485299

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： AKM Shaestagir CHOWDHURY ,  Debashish BASU ,  Githin F. ALAPATT ,  Justin E. MUELLER ,  James Y. JEONG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.