公开(公告)号：US20250113580A1

公开(公告)日：2025-04-03

申请号：US18374528

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Leonard Guler ,  Shaun Mills ,  Joseph D'Silva ,  Ehren Mannebach ,  Mauro Kobrinsky ,  Charles H. Wallace ,  Kalpesh Mahajan ,  Vivek Vishwakarma ,  Dincer Unluer ,  Jessica Panella

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.