公开(公告)号：US20180004597A1

公开(公告)日：2018-01-04

申请号：US15197590

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Kon-Woo KWON ,  Vivek KOZHIKKOTTU ,  Dinesh SOMASEKHAR

IPC: G06F11/10 ,  G11C11/4091 ,  G06F3/06 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C29/024 ,  G11C29/42

Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.