公开(公告)号：US20210216452A1

公开(公告)日：2021-07-15

申请号：US17214818

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Sai Prashanth MURALIDHARA ,  Alaa R. ALAMELDEEN ,  Rajat AGARWAL ,  Wei P. CHEN ,  Vivek KOZHIKKOTTU

IPC: G06F12/0802 ,  G06F3/06

Abstract: A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a “swap” manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.

公开(公告)号：US20170371791A1

公开(公告)日：2017-12-28

申请号：US15195887

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Ashish RANJAN ,  Vivek KOZHIKKOTTU

IPC: G06F12/0862 ,  G06F12/0842 ,  G11C11/408 ,  G11C11/4096 ,  G06F12/0866 ,  G11C11/4076

CPC classification number: G06F12/0862 ,  G06F12/0842 ,  G06F12/0866 ,  G06F2212/1016 ,  G06F2212/312 ,  G06F2212/602 ,  G06F2212/6022 ,  G11C2207/107

Abstract: An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.

公开(公告)号：US20200019513A1

公开(公告)日：2020-01-16

申请号：US16584612

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Vivek KOZHIKKOTTU ,  Suresh CHITTOR ,  Esha CHOUKSE ,  Shankar Ganesh RAMASUBRAMANIAN

IPC: G06F12/1045 ,  G06F12/06 ,  G06F12/02 ,  G06F11/30 ,  G06F13/16

Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.

公开(公告)号：US20190332469A1

公开(公告)日：2019-10-31

申请号：US16504199

申请日：2019-07-05

Applicant: INTEL CORPORATION

Inventor： Amir A. RADJAI ,  Nagi ABOULENEIN ,  Steve L. GEIGER ,  Satyajit A. JADHAV ,  Bezan J. KAPADIA ,  Vivek KOZHIKKOTTU ,  Rashmi LAKKUR SUBRAMANYAM ,  Srithar RAMESH ,  James M. SHEHADI ,  Jason D. VAN DYKEN

IPC: G06F11/10 ,  G06F13/16 ,  G06F9/38 ,  G06F9/54

Abstract: An in-band error correcting code (ECC) module intercepts input/output (I/O) operations directed to a memory. The in-band ECC module determines whether the I/O is directed to data that needs to be protected against error. In response to determining that the I/O is directed to data that needs to be protected against error, the in-band ECC module directs a memory controller to store or access ECC data corresponding to the data in a first preassigned area of the memory, and to store or access the data in a second preassigned area of the memory.

公开(公告)号：US20180004597A1

公开(公告)日：2018-01-04

申请号：US15197590

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Kon-Woo KWON ,  Vivek KOZHIKKOTTU ,  Dinesh SOMASEKHAR

IPC: G06F11/10 ,  G11C11/4091 ,  G06F3/06 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C29/024 ,  G11C29/42

Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.