公开(公告)号：US11626161B2

公开(公告)日：2023-04-11

申请号：US17368634

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Kyung Jean Yoon ,  John Gorman ,  Dany-Sebastien Ly-Gagnon

IPC: G11C16/10 ,  G11C13/00 ,  G11C11/56

Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.

公开(公告)号：US11100987B1

公开(公告)日：2021-08-24

申请号：US16831639

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Kyung Jean Yoon ,  John Gorman ,  Dany-Sebastien Ly-Gagnon

IPC: G11C13/00 ,  G11C11/56

Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.