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    Selection scheme for crosspoint memory
    3.
    发明授权
    Selection scheme for crosspoint memory 有权

    公开(公告)号：US11626161B2

    公开(公告)日：2023-04-11

    申请号：US17368634

    申请日：2021-07-06

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kyung Jean Yoon ,  John Gorman ,  Dany-Sebastien Ly-Gagnon

    IPC: G11C16/10 ,  G11C13/00 ,  G11C11/56

    Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.

    Multi-level cell (MLC) techniques and circuits for cross-point memory
    4.
    发明授权
    Multi-level cell (MLC) techniques and circuits for cross-point memory 有权

    公开(公告)号：US10957387B1

    公开(公告)日：2021-03-23

    申请号：US16687468

    申请日：2019-11-18

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kiran Pangal ,  Sanjay Rangan

    IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a third read voltage with a greater magnitude is applied across the memory cell. In one example, the thresholding of the memory cell triggers the application of a write current to write back the state of the bit due to read disturb from the read.

    Memory device with increased electrode resistance to reduce transient selection current
    8.
    发明授权
    Memory device with increased electrode resistance to reduce transient selection current 有权

    公开(公告)号：US11264567B2

    公开(公告)日：2022-03-01

    申请号：US16688309

    申请日：2019-11-19

    Applicant: INTEL CORPORATION

    Inventor： Srivatsan Venkatesan ,  Davide Mantegazza ,  John Gorman ,  Iniyan Soundappa Elango ,  Davide Fugazza ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

    High current fast read scheme for crosspoint memory
    9.
    发明授权
    High current fast read scheme for crosspoint memory 有权

    公开(公告)号：US11087854B1

    公开(公告)日：2021-08-10

    申请号：US16810127

    申请日：2020-03-05

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza

    IPC: G11C7/00 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C11/4091 ,  G11C11/408 ,  G11C16/26

    Abstract: A high current fast read scheme can enable improved read disturb without negatively impacting read performance. In one example, a fast read scheme involves applying a higher current as soon as the cell thresholds. In one example, circuitry detects the threshold event and turns on a bypass control transistor to bypass the circuitry applying the read voltage to enable a higher voltage and therefore higher current as soon as possible. The read time can thus be decreased (or at least not increased) and read disturb improved.

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