公开(公告)号：US20160189327A1

公开(公告)日：2016-06-30

申请号：US14583300

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  SHUBH B. SHAH ,  ASHUTOSH GARG ,  JIN XU ,  THOMAS A. PIAZZA ,  JORGE F. GARCIA PABON ,  MICHAEL K. DWYER

IPC: G06T1/20 ,  G09G5/00 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/30181 ,  G06T15/80 ,  G09G5/00 ,  G09G5/001 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/08

Abstract: Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

Abstract translation: 系统和方法可以提供图形处理器，其可以识别与在其他操作条件下执行指令时相比，某些浮点指令可以利用较少的硬件资源的功率的操作条件。 操作条件可以通过检查给定指令中使用的操作数来确定，包括操作数的相对大小以及操作数是否可以被视为等于某些定义的值。 浮点指令可以包括用于加法运算，乘法运算，比较运算和/或融合乘法运算的指令。

公开(公告)号：US20160026494A1

公开(公告)日：2016-01-28

申请号：US14338729

申请日：2014-07-23

Applicant: Intel Corporation

Inventor： BRIAN D. RAUCHFUSS ,  NAVEEN R. MATAM ,  MICHAEL K. DWYER ,  ADITYA NAVALE

IPC: G06F9/46 ,  G06F12/10 ,  G06F9/48

CPC classification number: G06F9/461 ,  G06F9/4812 ,  G06F12/1081 ,  G06F2212/2532

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与软件辅助上下文切换的中线优先级有关的方法和设备。 在一个实施例中，在图形处理单元（GPU）上执行的一个或多个线程响应于预先排除一个或多个线程的请求而以指令级粒度停止。 响应于指令级粒度和/或一个或多个指令的一个或多个线程的完成，一个或多个线程的上下文数据被复制到存储器。 还公开并要求保护其他实施例。