公开(公告)号：US20160189327A1

公开(公告)日：2016-06-30

申请号：US14583300

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  SHUBH B. SHAH ,  ASHUTOSH GARG ,  JIN XU ,  THOMAS A. PIAZZA ,  JORGE F. GARCIA PABON ,  MICHAEL K. DWYER

IPC: G06T1/20 ,  G09G5/00 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/30181 ,  G06T15/80 ,  G09G5/00 ,  G09G5/001 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/08

Abstract: Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

Abstract translation: 系统和方法可以提供图形处理器，其可以识别与在其他操作条件下执行指令时相比，某些浮点指令可以利用较少的硬件资源的功率的操作条件。 操作条件可以通过检查给定指令中使用的操作数来确定，包括操作数的相对大小以及操作数是否可以被视为等于某些定义的值。 浮点指令可以包括用于加法运算，乘法运算，比较运算和/或融合乘法运算的指令。

公开(公告)号：US20150287234A1

公开(公告)日：2015-10-08

申请号：US14741121

申请日：2015-06-16

Applicant: INTEL CORPORATION

Inventor： PETER L. DOYLE ,  THOMAS A. PIAZZA

IPC: G06T15/00 ,  G06T17/10 ,  G06T1/60 ,  G06T17/20

CPC classification number: G06T1/60 ,  G06T15/005 ,  G06T17/20

Abstract: An apparatus may include a memory to store a set of triangle vertices in a triangle, a processor circuit coupled to the memory and a cache to cache a set of triangle vertex indices corresponding to triangle vertices most recently transmitted through a graphics pipeline. The apparatus may also include an autostrip vertex processing component operative on the processor circuit to receive from the memory the set of triangle vertices, compare an index for each vertex of the set of triangle vertices to determine matches to the set of cached triangle vertex indices, and shift a single vertex index into the cache, the single vertex index corresponding to a vertex miss in which a given vertex of the set of triangle vertices does not match any vertex index of the set of cached triangle vertex indices when exactly two matches to the set of cached triangle vertex indices are found.

Abstract translation: 装置可以包括存储器，用于存储三角形中的一组三角形顶点，耦合到存储器的处理器电路和高速缓存，以缓存对应于最近通过图形管线传输的三角形顶点的一组三角形顶点索引。 该装置还可以包括在处理器电路上操作以从存储器接收该组三角形顶点的自动条带顶点处理组件，比较该组三角形顶点的每个顶点的索引，以确定与该组缓存的三角形顶点索引的匹配， 并将单个顶点索引移动到高速缓存中，对应于顶点未​​命中的单个顶点索引，其中三角形顶点集合的给定顶点与该组高速缓存的三角形顶点索引的任何顶点索引不匹配，当恰好两个匹配时 找到一组缓存的三角形顶点索引。

公开(公告)号：US20160180585A1

公开(公告)日：2016-06-23

申请号：US14581701

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： SUBRAMANIAM MAIYURAN ,  THOMAS A. PIAZZA ,  JORGE F. GARCIA PABON ,  SHUBH B. SHAH

IPC: G06T17/10 ,  G06K9/46

CPC classification number: G06K9/4604 ,  G06T15/005 ,  G06T2210/12

Abstract: An apparatus and method are described for a high throughput rasterizer. For example, one embodiment of an apparatus comprises: block selection logic to select a plurality of pixel blocks associated with edges of a primitive, the plurality of pixel blocks selected based on the pixel blocks having samples which are both inside and outside of the primitive; and edge determination logic to analyze samples of the plurality of pixel blocks selected by the block selection logic and responsively generate data identifying each edge of the primitive; and final mask determination logic to combine the data identifying each edge and generate a final mask representing the primitive.

Abstract translation: 为高通量光栅化器描述了一种装置和方法。 例如，装置的一个实施例包括：块选择逻辑，用于选择与图元的边缘相关联的多个像素块，所述多个像素块基于具有在图元内部和外部的样本的像素块来选择; 以及边缘确定逻辑来分析由块选择逻辑选择的多个像素块的样本，并且响应地生成识别图元的每个边缘的数据; 以及最终掩模确定逻辑，以组合识别每个边缘的数据，并生成表示原始图案的最终掩模。