公开(公告)号：US08929157B2

公开(公告)日：2015-01-06

申请号：US13680604

申请日：2012-11-19

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Navindra Navaratnam ,  Mahmoud Elassal

IPC: G11C7/00 ,  G05F1/10 ,  G11C5/14

CPC classification number: G05F1/10 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/105 ,  H02M3/07 ,  H02M2003/1566

Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.

Abstract translation: 电路提供电源电压。 电压调节器被耦合以接收目标参考信号。 电压调节器产生电源电压（Vtt）并被耦合以接收电源电压作为输入信号。 当电源电压超过上限阈值时，上限比较器接收高于目标参考电压信号和电源电压的上限电压信号，以产生“过高”信号。 下限比较器接收低于目标参考电压信号的下限电压信号和电源电压，以在电源电压低于下阈值时产生“太低”信号。 耦合上拉电流源以响应于太低的信号将电源电压拉高。 耦合下拉电流源以响应于太高的信号而将电源电压降低。

公开(公告)号：US20210167014A1

公开(公告)日：2021-06-03

申请号：US17177055

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Kushal Sreedhar ,  Christopher Mozak ,  Mahmoud Elassal

IPC: H01L23/528 ,  H01L23/522

Abstract: A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.

公开(公告)号：US12230569B2

公开(公告)日：2025-02-18

申请号：US17177055

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Kushal Sreedhar ,  Christopher Mozak ,  Mahmoud Elassal

IPC: H01L23/528 ,  H01L23/522 ,  G11C5/14 ,  G11C11/16

Abstract: A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.

公开(公告)号：US11916554B2

公开(公告)日：2024-02-27

申请号：US16716234

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Ralph S. Li ,  Chin Wah Lim ,  Mahmoud Elassal ,  Anant Balakrishnan ,  Isaac Ali

IPC: H03K3/00 ,  G06F11/16 ,  H03K3/017 ,  H03K5/135 ,  H03K5/156 ,  H03L7/081

CPC classification number: H03K3/017 ,  G06F11/1679 ,  H03K5/135 ,  H03K5/1565 ,  H03L7/0816

Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.