公开(公告)号：US20200334038A1

公开(公告)日：2020-10-22

申请号：US16921838

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Mark A. ANDERS ,  Himanshu KAUL ,  Sanu MATHEW

IPC: G06F9/30 ,  G06F17/16 ,  G06N20/00 ,  G06N3/063

Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

公开(公告)号：US20250165424A1

公开(公告)日：2025-05-22

申请号：US19033343

申请日：2025-01-21

Applicant: Intel Corporation

Inventor： Himanshu KAUL ,  Mark A. ANDERS ,  Gregory K. CHEN

IPC: G06F13/40 ,  H04L12/54 ,  H04L49/10 ,  H04L49/112

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

公开(公告)号：US20170139948A1

公开(公告)日：2017-05-18

申请号：US14944828

申请日：2015-11-18

Applicant: Intel Corporation

Inventor： Himanshu KAUL ,  Mark A. ANDERS ,  Sanu K. MATHEW

IPC: G06F17/30

CPC classification number: G06F17/10 ,  G06F17/30979 ,  G06K9/00986 ,  G06K9/6276

Abstract: Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.