公开(公告)号：US20180089642A1

公开(公告)日：2018-03-29

申请号：US15274200

申请日：2016-09-23

申请人： Intel Corporation

发明人： Vikram SURESH ,  Sudhir SATPATHY ,  Sanu MATHEW

IPC分类号： G06Q20/06 ,  H04L9/06 ,  G06F9/48

CPC分类号： G06Q20/0658 ,  G06F9/4881 ,  G06Q20/02 ,  G06Q20/3827 ,  G06Q2220/00 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/125 ,  H04L2209/38 ,  H04L2209/56 ,  Y02D10/24

摘要： A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi−1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.

公开(公告)号：US20190386815A1

公开(公告)日：2019-12-19

申请号：US16010206

申请日：2018-06-15

申请人： Intel Corporation

发明人： Sudhir SATPATHY ,  Vikram SURESH ,  Sanu MATHEW

IPC分类号： H04L9/06 ,  G09C1/00 ,  G06F7/72

摘要： Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

公开(公告)号：US20200334038A1

公开(公告)日：2020-10-22

申请号：US16921838

申请日：2020-07-06

申请人： Intel Corporation

发明人： Mark A. ANDERS ,  Himanshu KAUL ,  Sanu MATHEW

IPC分类号： G06F9/30 ,  G06F17/16 ,  G06N20/00 ,  G06N3/063

摘要： Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

公开(公告)号：US20170373839A1

公开(公告)日：2017-12-28

申请号：US15192739

申请日：2016-06-24

申请人： Intel Corporation

发明人： Vikram SURESH ,  Sudhir SATPATHY ,  Sanu MATHEW ,  Neeraj UPASANI

IPC分类号： H04L9/06 ,  G06F13/16 ,  G06F21/44 ,  G06F12/1009 ,  G06F13/42 ,  G06F12/14

CPC分类号： G06F13/4282 ,  G06F12/1009 ,  G06F12/1408 ,  G06F12/1425 ,  G06F13/1668 ,  G06F21/44 ,  G06F21/575 ,  G06F21/76 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/402 ,  G09C1/00 ,  H04L9/0618 ,  H04L9/3239

摘要： Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.

公开(公告)号：US20180062829A1

公开(公告)日：2018-03-01

申请号：US15252741

申请日：2016-08-31

申请人： Intel Corporation

发明人： Vikram SURESH ,  Sudhir SATPATHY ,  Sanu MATHEW

IPC分类号： H04L9/06

CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G09C1/00 ,  H04L9/0637 ,  H04L2209/12 ,  H04L2209/24

摘要： A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.