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    UNIFIED AES-SMS4-CAMELLIA SYMMETRIC KEY BLOCK CIPHER ACCELERATION
    2.
    发明申请
    UNIFIED AES-SMS4-CAMELLIA SYMMETRIC KEY BLOCK CIPHER ACCELERATION 审中-公开

    公开(公告)号：US20190386815A1

    公开(公告)日：2019-12-19

    申请号：US16010206

    申请日：2018-06-15

    Applicant: Intel Corporation

    Inventor： Sudhir SATPATHY ,  Vikram SURESH ,  Sanu MATHEW

    IPC: H04L9/06 ,  G09C1/00 ,  G06F7/72

    Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

    HYBRID AES-SMS4 HARDWARE ACCELERATOR
    3.
    发明申请
    HYBRID AES-SMS4 HARDWARE ACCELERATOR 审中-公开

    公开(公告)号：US20180062829A1

    公开(公告)日：2018-03-01

    申请号：US15252741

    申请日：2016-08-31

    Applicant: Intel Corporation

    Inventor： Vikram SURESH ,  Sudhir SATPATHY ,  Sanu MATHEW

    IPC: H04L9/06

    CPC classification number: H04L9/0631 ,  G06F9/30007 ,  G09C1/00 ,  H04L9/0637 ,  H04L2209/12 ,  H04L2209/24

    Abstract: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.

    FULLY HOMOMORPHIC ENCRYPTION
    4.
    发明申请
    FULLY HOMOMORPHIC ENCRYPTION 有权

    公开(公告)号：US20250007687A1

    公开(公告)日：2025-01-02

    申请号：US18217551

    申请日：2023-07-01

    Applicant: Intel Corporation

    Inventor： Sanu MATHEW ,  Vikram SURESH ,  Sachin TANEJA ,  Raghavan KUMAR ,  Christopher WILKERSON

    IPC: H04L9/00

    Abstract: Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.

    VARIABLE FORMAT, VARIABLE SPARSITY MATRIX MULTIPLICATION INSTRUCTION
    5.
    发明申请
    VARIABLE FORMAT, VARIABLE SPARSITY MATRIX MULTIPLICATION INSTRUCTION 审中-公开

    公开(公告)号：US20200334038A1

    公开(公告)日：2020-10-22

    申请号：US16921838

    申请日：2020-07-06

    Applicant: Intel Corporation

    Inventor： Mark A. ANDERS ,  Himanshu KAUL ,  Sanu MATHEW

    IPC: G06F9/30 ,  G06F17/16 ,  G06N20/00 ,  G06N3/063

    Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

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