公开(公告)号：US20230194997A1

公开(公告)日：2023-06-22

申请号：US17558417

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mark Phillips ,  Shakul Tandon

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70475 ,  G03F7/70741 ,  G03F7/70466

Abstract: Reticles, line feature patterns, and methods are described related to improving overlay margins in reticle stitching applications. A first reticle to expose a first field includes a first portion of a line feature. The first portion has a pattern inclusive of one or more pattern features. The first reticle or a second reticle to expose a second field adjacent the first filed includes a second portion of the line feature. The second portion has an inverse pattern relative to the first pattern such that, when the first and inverse patterns are overlaid, a continuous merged region is formed.

公开(公告)号：US20230207491A1

公开(公告)日：2023-06-29

申请号：US17561353

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Kimberly Pierce ,  Marni Nabors ,  Mark Phillips

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06 ,  G03F7/20

CPC classification number: H01L23/585 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0611 ,  G03F7/2004

Abstract: Devices, systems, and methods are described related to providing nonlinear lithographic seams, such as rectilinear lithographic seams, between adjacent fields of an integrated circuit die. Such nonlinear lithographic seams include lithographic enabling structures formed in co-planar layers with respect to functional structures in functional units of the fields of the integrated circuit die. Providing nonlinear lithographic seams improves layout efficiency of the functional units of the integrated circuit die.