公开(公告)号：US10282322B2

公开(公告)日：2019-05-07

申请号：US15482542

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukuman P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0897 ,  G06F9/46 ,  G06F13/40 ,  G06F12/02 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.