公开(公告)号：US20220116487A1

公开(公告)日：2022-04-14

申请号：US17556089

申请日：2021-12-20

申请人： Intel Corporation

发明人： Naru Dames SUNDAR ,  Chih-Jen CHANG

IPC分类号： H04L69/22

摘要： A stacked memory such as a high bandwidth memory (HBM) with a wide data path is used by a streaming pipeline in a network interface controller to buffer segments of a data packet to allow the network interface controller to perform operations on the packet payload. The headers and packet payload can be scanned and classified concurrently with the buffered payload parsed in parallel.

公开(公告)号：US20220103530A1

公开(公告)日：2022-03-31

申请号：US17544699

申请日：2021-12-07

申请人： Intel Corporation

发明人： Daniel DALY ,  Anjali Singhai JAIN ,  Yadong LI ,  Stephen DOYLE ,  Naru Dames SUNDAR ,  Chih-Jen CHANG ,  Sailesh BISSESSUR ,  Andrew CUNNINGHAM ,  Edwin VERPLANKE ,  Patrick FLEMING

IPC分类号： H04L9/08

摘要： Examples described herein relate to a network interface device that includes circuitry, configured to perform encryption of data, generate one or more packets from the encrypted data, cause transmission of the one or more packets with the encrypted data, manage reliability of transport of the transmitted one or more packets with the encrypted data, and share protocol state information between a host system and the network interface device using connectivity based on user space accessible queues.

公开(公告)号：US20210288910A1

公开(公告)日：2021-09-16

申请号：US17332815

申请日：2021-05-27

申请人： Intel Corporation

发明人： Daniel DALY ,  Anjali Singhai JAIN ,  Chih-Jen CHANG ,  Edmund CHEN ,  Robert HATHAWAY ,  Naru Dames SUNDAR ,  Pawel SZYMANSKI ,  John MANGAN

IPC分类号： H04L12/815 ,  H04L12/851 ,  H04L12/935

摘要： Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS). In some examples, the circuitry is to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on H-QoS comprises a programmable packet processing pipeline that is to be configured to perform one or more of: packet drops of packets received in excess of a receive rate, packet drops based on packet transmission in excess of a transmit rate, and/or traffic shaping of the received packets prior to transmission through one or more output ports. In some examples, to perform packet drops of packets received in excess of a receive rate, the programmable packet processing pipeline is to perform rate limiting per one or more of: class of service, subscriber, service, or interface.