PROCESSOR RELATED COMMUNICATIONS
    3.
    发明申请

    公开(公告)号:US20190207868A1

    公开(公告)日:2019-07-04

    申请号:US16276979

    申请日:2019-02-15

    申请人: Intel Corporation

    摘要: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

    PAGE FAULT MANAGEMENT TECHNOLOGIES

    公开(公告)号:US20220197805A1

    公开(公告)日:2022-06-23

    申请号:US17479954

    申请日:2021-09-20

    申请人: Intel Corporation

    摘要: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.

    NETWORK INTERFACE DEVICE WITH SUPPORT FOR HIERARCHICAL QUALITY OF SERVICE (QOS)

    公开(公告)号:US20210288910A1

    公开(公告)日:2021-09-16

    申请号:US17332815

    申请日:2021-05-27

    申请人: Intel Corporation

    摘要: Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS). In some examples, the circuitry is to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on H-QoS comprises a programmable packet processing pipeline that is to be configured to perform one or more of: packet drops of packets received in excess of a receive rate, packet drops based on packet transmission in excess of a transmit rate, and/or traffic shaping of the received packets prior to transmission through one or more output ports. In some examples, to perform packet drops of packets received in excess of a receive rate, the programmable packet processing pipeline is to perform rate limiting per one or more of: class of service, subscriber, service, or interface.