公开(公告)号：US20220303230A1

公开(公告)日：2022-09-22

申请号：US17830814

申请日：2022-06-02

申请人： Intel Corporation

发明人： Ping YU ,  Sarig LIVNE ,  Qi ZHANG ,  Xuan DING ,  Raul DIAZ ,  Pawel SZYMANSKI

IPC分类号： H04L49/90 ,  H04L69/22 ,  H04L49/00 ,  H04L69/16 ,  H04L69/166

摘要： Examples described herein relate to a network interface device to perform header splitting with payload reordering for one or more packets received at the network interface device and copy headers and/or payloads associated with the one or more packets to at least one memory device.

公开(公告)号：US20210326285A1

公开(公告)日：2021-10-21

申请号：US17207135

申请日：2021-03-19

申请人： Intel Corporation

发明人： Balaji PARTHASARATHY ,  Ramamurthy KRITHIVAS ,  Bradley A. BURRES ,  Pawel SZYMANSKI ,  Yi-Feng LIU

IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US20230367729A1

公开(公告)日：2023-11-16

申请号：US18199042

申请日：2023-05-18

申请人： Intel Corporation

发明人： Balaji PARTHASARATHY ,  Ramamurthy KRITHIVAS ,  Bradley BURRES ,  Pawel SZYMANSKI ,  Yi-Feng LIU

IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

CPC分类号： G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US20210288910A1

公开(公告)日：2021-09-16

申请号：US17332815

申请日：2021-05-27

申请人： Intel Corporation

发明人： Daniel DALY ,  Anjali Singhai JAIN ,  Chih-Jen CHANG ,  Edmund CHEN ,  Robert HATHAWAY ,  Naru Dames SUNDAR ,  Pawel SZYMANSKI ,  John MANGAN

IPC分类号： H04L12/815 ,  H04L12/851 ,  H04L12/935

摘要： Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS). In some examples, the circuitry is to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on H-QoS comprises a programmable packet processing pipeline that is to be configured to perform one or more of: packet drops of packets received in excess of a receive rate, packet drops based on packet transmission in excess of a transmit rate, and/or traffic shaping of the received packets prior to transmission through one or more output ports. In some examples, to perform packet drops of packets received in excess of a receive rate, the programmable packet processing pipeline is to perform rate limiting per one or more of: class of service, subscriber, service, or interface.