公开(公告)号：US20170373839A1

公开(公告)日：2017-12-28

申请号：US15192739

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Vikram SURESH ,  Sudhir SATPATHY ,  Sanu MATHEW ,  Neeraj UPASANI

IPC: H04L9/06 ,  G06F13/16 ,  G06F21/44 ,  G06F12/1009 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F13/4282 ,  G06F12/1009 ,  G06F12/1408 ,  G06F12/1425 ,  G06F13/1668 ,  G06F21/44 ,  G06F21/575 ,  G06F21/76 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/402 ,  G09C1/00 ,  H04L9/0618 ,  H04L9/3239

Abstract: Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.