公开(公告)号：US20240220410A1

公开(公告)日：2024-07-04

申请号：US18089757

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Prasanna Pandit ,  Neetu Jindal ,  Israel Diamand ,  Asaf Rubinstein ,  Leon Polishuk ,  Oz Shitrit

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/62

Abstract: Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed.

公开(公告)号：US12130739B2

公开(公告)日：2024-10-29

申请号：US16833304

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/0831 ,  G06F12/123 ,  G06F2212/1021

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

公开(公告)号：US20210303467A1

公开(公告)日：2021-09-30

申请号：US16833304

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC: G06F12/0811 ,  G06F12/0831 ,  G06F12/123

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.