公开(公告)号：US20240220410A1

公开(公告)日：2024-07-04

申请号：US18089757

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Prasanna Pandit ,  Neetu Jindal ,  Israel Diamand ,  Asaf Rubinstein ,  Leon Polishuk ,  Oz Shitrit

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/62

Abstract: Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed.