公开(公告)号：US20230086149A1

公开(公告)日：2023-03-23

申请号：US17483491

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Anoop Mukker ,  Arik Gihon ,  Zvika Greenfield ,  Asaf Rubinstein ,  Leo Aqrabawi

IPC: G06F12/0804 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3287

Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.

公开(公告)号：US20170285703A1

公开(公告)日：2017-10-05

申请号：US15623536

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US20160252952A1

公开(公告)日：2016-09-01

申请号：US14634777

申请日：2015-02-28

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括耦合到第一核的第一核和电源管理代理（PMA），以包括存储操作列表的静态表，以及多个列，以指定包括 相应的操作子集。 每个流的执行与第一核的相应状态相关联。 PMA包括控制寄存器（CR），其包括多个存储元件以接收第一值和第二值中的一个。 处理器包括执行逻辑，响应于将第一核放入第一状态的命令，当对应的存储元件存储第一值时，执行第一流的操作，并且当第一流处于 相应的元素存储第二个值。 描述和要求保护其他实施例。

公开(公告)号：US10915453B2

公开(公告)日：2021-02-09

申请号：US15394550

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Israel Diamand ,  Zvika Greenfield ,  Julius Mandelblat ,  Asaf Rubinstein

IPC: G06F12/0893 ,  G06F12/0884 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/128

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

公开(公告)号：US10324718B2

公开(公告)日：2019-06-18

申请号：US15864158

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal San Andrian ,  Suleyman Sair ,  Bret L. Toll ,  Zeev Sperber ,  Amit Gradstein ,  Asaf Rubinstein

IPC: G06F9/30

Abstract: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US09846648B2

公开(公告)日：2017-12-19

申请号：US14709323

申请日：2015-05-11

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Anant V. Nori ,  Supratik Majumder ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/0864 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/123

CPC classification number: G06F12/0864 ,  G06F12/0851 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  Y02D10/13

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

公开(公告)号：US20170109163A1

公开(公告)日：2017-04-20

申请号：US15391695

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Asaf Rubinstein ,  Tom Aviram

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3887 ,  G06F9/3889 ,  G06F15/8007

Abstract: Vector single instruction multiple data (SIMD) shift and rotate instructions are provided specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, and a second vector register. Vector data fields of a first element size are duplicated. Duplicate vector data fields are stored as corresponding data fields of twice the first element size. Control logic receives an element size for performing a SIMD shift or rotation operation. Through selectors corresponding to a vector element, portions are selected from the duplicated data fields, the selectors corresponding to any particular vector element select all portions similarly from the duplicated data fields for that particular vector element responsive to the first element size, but selectors corresponding to any particular vector element select at least two portions from the duplicated data fields differently for that particular vector element responsive to a second element size.

公开(公告)号：US10761594B2

公开(公告)日：2020-09-01

申请号：US15623536

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/324

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US10657070B2

公开(公告)日：2020-05-19

申请号：US16105434

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Blaise Fanning ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/123 ,  G06F12/0891 ,  G06F12/0897

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.

公开(公告)号：US10153784B2

公开(公告)日：2018-12-11

申请号：US15412763

申请日：2017-01-23

Applicant: INTEL CORPORATION

Inventor： Daniel Greenspan ,  Asaf Rubinstein ,  Julius Yuli Mandelblat

IPC: H03M13/29 ,  H03M13/05 ,  H03M13/45 ,  G06F11/10 ,  H03M13/19

Abstract: Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).