公开(公告)号：US20220415380A1

公开(公告)日：2022-12-29

申请号：US17357466

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Naveen Prabhu Vittal Prabhu ,  Aliasgar S. Madraswala ,  Bharat Pathak ,  Binh Ngo ,  Netra Mahuli ,  Ahsanur Rahman

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

公开(公告)号：US11693582B2

公开(公告)日：2023-07-04

申请号：US16947592

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Ali Khakifirooz ,  Camila Jaramillo ,  John Egler ,  Netra Mahuli ,  Renjie Chen ,  Yogesh Wakchaure

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.