公开(公告)号：US11693582B2

公开(公告)日：2023-07-04

申请号：US16947592

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Ali Khakifirooz ,  Camila Jaramillo ,  John Egler ,  Netra Mahuli ,  Renjie Chen ,  Yogesh Wakchaure

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.

公开(公告)号：US20210294698A1

公开(公告)日：2021-09-23

申请号：US17342993

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  George Kalwitz ,  Anand Ramalingam ,  Ravi Motwani ,  Renjie Chen

IPC: G06F11/10 ,  H03M13/45 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.