公开(公告)号：US08860479B2

公开(公告)日：2014-10-14

申请号：US13929164

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Choupin Huang ,  Vijaya K. Boddu ,  Stefan Rusu ,  Nicholas B Peterson

IPC: H03L7/06 ,  H03L7/07 ,  H03L7/089 ,  H03L7/08

CPC classification number: H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.

Abstract translation: 集成时钟差分缓冲。 具有第一时钟比率的第一锁相环（PLL）电路被耦合以接收输入差分时钟信号。 第一PLL电路产生第一参考时钟信号。 具有第二时钟比的第二PLL电路被耦合以接收输入差分时钟信号。 第二个PLL电路产生第二个参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应于第一参考时钟信号的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供对应于第二参考时钟信号的第二差分参考时钟信号。 第一PLL电路，第二PLL电路，第一组输出缓冲器和第二组输出缓冲器驻留在还具有至少接收第一差分参考时钟信号的管芯的集成电路封装中。

公开(公告)号：US09385728B2

公开(公告)日：2016-07-05

申请号：US14513024

申请日：2014-10-13

Applicant: Intel Corporation

Inventor： Choupin Huang ,  Vijaya K. Boddu ,  Stefan Rusu ,  Nicholas B Peterson

IPC: H03L7/07 ,  G06F3/16 ,  H03L7/089 ,  H03L7/08

CPC classification number: H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.

Abstract translation: 集成时钟差分缓冲。 具有第一时钟比率的第一锁相环（PLL）电路被耦合以接收输入差分时钟信号。 第一PLL电路产生第一参考时钟信号。 具有第二时钟比的第二PLL电路被耦合以接收输入差分时钟信号。 第二个PLL电路产生第二个参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应于第一参考时钟信号的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供对应于第二参考时钟信号的第二差分参考时钟信号。 第一PLL电路，第二PLL电路，第一组输出缓冲器和第二组输出缓冲器驻留在还具有至少接收第一差分参考时钟信号的管芯的集成电路封装中。