公开(公告)号：US20240332290A1

公开(公告)日：2024-10-03

申请号：US18129700

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Patrick Morrow ,  Nikhil Mehta ,  Leonard Guler ,  Sudipto Naskar ,  Alison Davis ,  Dan Lavric ,  Matthew Prince ,  Jeanne Luce ,  Charles Wallace ,  Cortnie Vogelsberg ,  Rajaram Pai ,  Caitlin Kilroy ,  Jojo Amonoo ,  Sean Pursel ,  Yulia Gotlib

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.