公开(公告)号：US20210193248A1

公开(公告)日：2021-06-24

申请号：US17132902

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Lunkai ZHANG ,  Rakan MADDAH ,  Prashant S. DAMLE

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/00

Abstract: A “near miss” based refresh scheme performs refreshes to read disturbed codewords proactively (or on-demand). In one example, a controller receives a read request to a target address (e.g., from a host memory controller). The read request is sent to memory, and the memory returns the read data. ECC logic decodes the read data and determines the number of error bits in the read data. If the number of error bits is greater than a threshold, a refresh write command is sent to the command queue. If an outstanding write command to the same address is already in the queue, the refresh write can be dropped and the outstanding write command converted into a refresh write command. A data cache can service read commands to the target address until the near miss-based refresh command completes.

公开(公告)号：US20210110862A1

公开(公告)日：2021-04-15

申请号：US17128963

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Akanksha MEHTA ,  Benjamin GRANIELLO ,  Rakan MADDAH ,  Philip HILLIER ,  Richard P. MANGOLD ,  Prashant S. DAMLE ,  Kunal A. KHOCHARE

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C15/04

Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.