公开(公告)号：US20190079836A1

公开(公告)日：2019-03-14

申请号：US16100133

申请日：2018-08-09

Applicant: INTEL CORPORATION

Inventor： Shaun M. MILLER ,  Richard P. MANGOLD

IPC: G06F11/16

Abstract: Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.

公开(公告)号：US20170177496A1

公开(公告)日：2017-06-22

申请号：US14972053

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Woojong HAN ,  Andy M. RUDOFF ,  Mark A. SCHMISSEUR ,  Richard P. MANGOLD

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F12/0238 ,  G06F12/0873 ,  G06F12/0877 ,  G06F12/0893 ,  G06F12/1441 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/312 ,  G06F2212/608 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

公开(公告)号：US20210110862A1

公开(公告)日：2021-04-15

申请号：US17128963

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Akanksha MEHTA ,  Benjamin GRANIELLO ,  Rakan MADDAH ,  Philip HILLIER ,  Richard P. MANGOLD ,  Prashant S. DAMLE ,  Kunal A. KHOCHARE

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C15/04

Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.

公开(公告)号：US20170177246A1

公开(公告)日：2017-06-22

申请号：US14976921

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Shaun M. MILLER ,  Richard P. MANGOLD

IPC: G06F3/06 ,  G06F11/20

CPC classification number: G06F11/1658 ,  G06F11/1666 ,  G06F11/20

Abstract: Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.