公开(公告)号：US20190057728A1

公开(公告)日：2019-02-21

申请号：US16036756

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Rakesh JEYASINGH ,  Nevil N GAJERA ,  Mase J. TAUB ,  Kiran PANGAL

IPC: G11C7/12 ,  G11C11/16 ,  G11C13/00

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.