公开(公告)号：US20190096482A1

公开(公告)日：2019-03-28

申请号：US16140441

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Raymond W. ZENG ,  Mase J. TAUB ,  Kiran PANGAL ,  Sandeep K. GULIANI

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/08 ,  G11C8/06

CPC classification number: G11C13/0028 ,  G11C8/06 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/3418 ,  G11C2013/0052 ,  G11C2013/0092

Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

公开(公告)号：US20170294228A1

公开(公告)日：2017-10-12

申请号：US15614141

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Mase J. TAUB ,  Sandeep K. GULIANI ,  Kiran PANGAL

IPC: G11C13/00 ,  G11C5/02

CPC classification number: G11C13/0004 ,  G11C5/02 ,  G11C7/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

公开(公告)号：US20190074058A1

公开(公告)日：2019-03-07

申请号：US16105922

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： Mase J. TAUB ,  Sandeep K. GULIANI ,  Kiran PANGAL

IPC: G11C13/00 ,  G11C7/00 ,  G11C5/02

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

公开(公告)号：US20220415425A1

公开(公告)日：2022-12-29

申请号：US17358421

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Hemant P. RAO ,  Raymond W. ZENG ,  Prashant S. DAMLE ,  Zion S. KWOK ,  Kiran PANGAL ,  Mase J. TAUB

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/50 ,  G11C7/06

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

公开(公告)号：US20190057728A1

公开(公告)日：2019-02-21

申请号：US16036756

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Rakesh JEYASINGH ,  Nevil N GAJERA ,  Mase J. TAUB ,  Kiran PANGAL

IPC: G11C7/12 ,  G11C11/16 ,  G11C13/00

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.