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    CURRENT DELIVERY AND SPIKE MITIGATION IN A MEMORY CELL ARRAY
    1.
    发明申请
    CURRENT DELIVERY AND SPIKE MITIGATION IN A MEMORY CELL ARRAY 审中-公开

    公开(公告)号：US20190043923A1

    公开(公告)日：2019-02-07

    申请号：US16145084

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Shafqat AHMED ,  Kiran PANGAL

    IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L27/11507 ,  H01L43/02 ,  H01L43/12

    Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.

    TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
    3.
    发明申请
    TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20190057728A1

    公开(公告)日：2019-02-21

    申请号：US16036756

    申请日：2018-07-16

    Applicant: Intel Corporation

    Inventor： Rakesh JEYASINGH ,  Nevil N GAJERA ,  Mase J. TAUB ,  Kiran PANGAL

    IPC: G11C7/12 ,  G11C11/16 ,  G11C13/00

    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

    MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
    4.
    发明申请
    MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20200035300A1

    公开(公告)日：2020-01-30

    申请号：US16593530

    申请日：2019-10-04

    Applicant: Intel Corporation

    Inventor： Sanjay RANGAN ,  Kiran PANGAL ,  Nevil N. GAJERA ,  Lu LIU ,  Gayathri RAO SUBBU

    IPC: G11C13/00 ,  G11C11/16 ,  G11C7/04 ,  H01L45/00

    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

    TECHNIQUES TO MITIGATE ERROR DURING A READ OPERATION TO A MEMORY ARRAY
    7.
    发明申请
    TECHNIQUES TO MITIGATE ERROR DURING A READ OPERATION TO A MEMORY ARRAY 有权

    公开(公告)号：US20210304817A1

    公开(公告)日：2021-09-30

    申请号：US16828860

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Davide MANTEGAZZA ,  Kiran PANGAL

    IPC: G11C13/00 ,  G11C29/12 ,  G11C29/50 ,  G11C29/44

    Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.

    CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
    10.
    发明申请
    CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE 审中-公开

    公开(公告)号：US20190074058A1

    公开(公告)日：2019-03-07

    申请号：US16105922

    申请日：2018-08-20

    Applicant: Intel Corporation

    Inventor： Mase J. TAUB ,  Sandeep K. GULIANI ,  Kiran PANGAL

    IPC: G11C13/00 ,  G11C7/00 ,  G11C5/02

    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

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