公开(公告)号：US08745464B2

公开(公告)日：2014-06-03

申请号：US13968266

申请日：2013-08-15

Applicant: Intel Corporation

Inventor： Ramesh Subashchandrabose ,  Tessil Thomas ,  Sambaran Mitra ,  Debaleena Das ,  Kai Cheng

IPC: H03M13/00 ,  G11C29/00 ,  G06F12/06 ,  H03M13/03 ,  G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H04L1/00 ,  G06F12/02 ,  G11C8/12

CPC classification number: H03M13/03 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1064 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/02 ,  G11C8/12 ,  G11C29/00 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H04L1/0061

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract translation: 本公开的实施例描述了用于在存储器系统中提供排名特定循环冗余校验的方法，装置和系统配置。

公开(公告)号：US20220199142A1

公开(公告)日：2022-06-23

申请号：US17131585

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Sambaran Mitra

IPC: G11C11/4074 ,  G11C11/4096 ,  G06F11/10

Abstract: Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. The hardware and/or software decreases the voltage level for the power supply and enables CRC to compensate signal errors (e.g., errors from signal integrity issues). Hardware and/or software dynamically adjusts voltage level of the power supply rail based on the throughput or speed of the DDR link. In some examples, depending on read or write operations, the voltage level of the power supply rail is adjusted.