公开(公告)号：US11327523B2

公开(公告)日：2022-05-10

申请号：US16799480

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Eyal Fayneh ,  Elias Nassar ,  Inbar Falkov ,  Ramkumar Krithivasan ,  Vijay K. Vuppaladadium ,  Miguel A. Corvacho Hernandez ,  Samer Nassar ,  Yair Talker

IPC: G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G06F1/12

Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

公开(公告)号：US10571953B2

公开(公告)日：2020-02-25

申请号：US15642109

申请日：2017-07-05

Applicant: Intel Corporation

Inventor： Eyal Fayneh ,  Elias Nassar ,  Inbar Falkov ,  Ramkumar Krithivasan ,  Vijay K. Vuppaladadium ,  Miguel A. Corvacho Hernandez ,  Samer Nasser ,  Yair Talker

IPC: G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G06F1/12

Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.